Conventionally, a structure in which a strain is generated in a channel in order to improve an on-current in a MOS transistor has been practically applied. For example, an n-channel MOS transistor covered with a film generating a tensile stress has been practically applied. Further, a p-channel MOS transistor having a SiGe layer formed in a source and a drain thereof has also been practically applied.
As described above, it is preferable to generate a strain in a tensile direction (a tensile strain) in a channel in an n-channel MOS transistor, and generate a strain in a compressive direction (a compressive strain) in a channel in a p-channel MOS transistor. Therefore, when manufacturing a semiconductor device having both an n-channel MOS transistor and a p-channel MOS transistor such as a CMOS transistor, in order to generate preferable strains in both of the transistors, it is necessary to perform processing separately. In this case, time and cost are increased significantly.
For example, in an SRAM (static random access memory) cell, as illustrated in FIG. 17, p-channel MOS transistors P1 and P2 having sources thereof connected to a power supply Vdd are provided, and n-channel MOS transistors N1 and N2 having sources thereof grounded are provided. Then, respective drains of the transistors P1 and N1 are connected to each other, and respective drains of the transistors P2 and N2 are connected to each other. That is, in the SRAM cell, two CMOS transistors are included. Further, an n-channel MOS transistor N3 having a gate connected to a word line W is connected between the CMOS transistor composed of the transistors P1 and N1 and a bit line /B, and an n-channel MOS transistor N4 having a gate connected to the word line W is connected between the CMOS transistor composed of the transistors P2 and N2 and a bit line B. Accordingly, the CMOS transistors are included in the SRAM cell.
Then, in a conventional SRAM cell, layouts as illustrated in FIG. 18 or FIG. 19 have been adopted. In either case, gates 105 and p-type impurity diffusion layers 107p are provided in transistors P1 and P2, and the gates 105 and n-type impurity diffusion layers 107n are provided in transistors N1 to N4. Then, the transistor P1 and the transistor N1 are disposed in parallel to each other, and the transistor P2 and the transistor N2 are disposed in parallel to each other. This is to share the gate between the two transistors constituting a CMOS transistor.
Therefore, when compressive strains are made to be generated in the transistors P1 and P2, compressive strains are also generated in the transistors N1 and N2. Then, when tensile strains are made to be generated in the transistors N1 and N2, tensile strains are also generated in the transistors P1 and P2.
Thus, in a conventional technique, it is not possible to improve both on-currents of the two transistors constituting the CMOS transistor. This is also obvious from description of Non-Patent Document 1 or the like.    Patent Document 1: Japanese Patent Application Laid-open No. 2004-335741    Patent Document 2: Japanese Patent Application Laid-open No. 2006-80161    Non-Patent Document 1: SSDM, pp. 14-15, 2002